A multi-threshold design can be achieved by employing carbon nanotubes (CNTs) with different diameters, as the threshold voltage of the carbon nanotube field effect transistor (CNTFET) depends on the diameter of the CNT. In this paper, this feature is exploited to design ternary logic circuits for achieving improved performance. We presented new design for CNTFET-based ternary combinational circuits such as half adder, full adder, half subtractor, full subtractor and comparator using negation of literals technique. Extensive simulation results using Synopsis HSPICE simulator demonstrate that using new technique 5–۱۴۵ times improvement in power delay product can be achieved with reduced gate count compared to the existing ternary–binary combinational gate design.
Multi-valued logic replaces the classical Boolean characterization of variables with either finitely or infinitely many values such as ternary logic  or fuzzy logic, since it reduces the number of signals involved in the communication increasing their information content, thereby reducing complexity of interconnects and chip area [2–۴]. Ultimate goal of using multi-valued logic over binary logic is that (i) Chip area can be reduced by transmitting more MVL information through each wire than binary (ii) Complexity of the circuit may be decreased since each MVL element can process more information than binary element and (iii) speed of serial information transmission can be faster since the transmitted information p.u time is increased. Ternary circuits may be of more theoretical significance than other MVL logics as (i) 3 is the smaller radix greater than binary and ternary functions and circuits have the simpler form and construction, (ii) the product of radix and the number of signals have impact on the cost or complexity of MVL circuits, ternary circuits will be more economical, (iii) the same hardware of balanced ternary logic (1, 0, −۱) is used for addition and subtraction, and (iv) 3 is not an integral power of 2, research on ternary logic may reveal design techniques that are overlooked in the study of binary or other MVL logic. By employing ternary logic, serial and serial parallel arithmetic operations can be carried out faster. In many cases, MVL logic has been combined with binary logic to enhance the performance of CMOS technologies . Three kinds of MVL circuits are current-mode, voltage-mode and mixedmode or hybrid mode. Several current-mode MVL circuits have been fabricated which show better performances compared to binary circuits [6–۸]. But the power consumption of current mode circuits is high due to their inherent nature of constant current flow during the operation. Voltage mode circuits consume a large current only during the logic level switching, thus offering less power consumption. The multi-valued logic design by itself is not enough in nanotechnology for speed of power improvements needed in digital systems, as a result new devices and circuits have been explored to replace silicon in nanoscale transistors. Among all, CNTFET is a promising alternative to replace conventional devices for low power and high performance design, due to its ballistic transport and low off current properties [9–۱۳]. The multi-threshold design depends on the transistor body effects that apply different bias voltages to the bulk terminal of the transistors. As the threshold voltage of a CNTFET is determined by the CNT diameter, a multi-threshold design can be achieved by employing CNTs with different diameters in the CNTFET model. The scope of this paper is to implement novel multi-valued logic design based on multi-threshold CNTFETs to explore the possibilities and advantages in realizing CNTFET circuits with reduced T-gates by employing negation of literals technique. In this paper, new design for CNTFET combinational circuits is proposed, described and assessed. Extensive simulation results using Synopsys HSPICE simulator demonstrate significant advantages of proposed design in terms of speed and power consumption compared with existing multi-valued logic design.